1. CPU Core - RDC proprietary
RISC architecture - Five-stage pipeline architecture - Operation
frequency: 150MHz - Supports a 16K-byte uniform cache
2. ROM/RAM/SDRAM Controller and Addressing
Space - Supports 16-bit data bus width - Flash ROM/SRAM
control interface - SDRAM control interface - 16M addressing
space - 64K-byte I/O space
3. Two Independent DMA Controllers
- Supports high-speed DMA transfers
4. Interrupt Controller - Provides
8 maskable external interrupt channels
5. Counter/Timers - Three independent
programmable 16-bit timers - One programmable watchdog timer
which can generate NMI or reset
6. High Performance UART Ports -
Supports 2 high performance UARTs with send/receive 16-byte
FIFOs - Programmable baud rate generator - The data rates
are programmable from 50 to 460.8K baud (max. to 1Mbps) -
The character options are programmable for 1 start bit; 1,
1.5 or 2 stop bits; even, odd or no parity, 5~8 data bits
7. RDC Debug Tool Support -
RDC debug tool with a JTAG-like interface
8. General Programmable I/O -
64 programmable I/O ports - Pins individually configurable
to input or output mode
9. Two 10/100M Fast Ethernet MAC Ports
- IEEE 802.3u MII interface - IEEE 802.3x flow control
in full-duplex mode - Internal loop-back self-test circuit
support - Descriptor architecture for packet TX/RX
10. PCI Control Interface Support -
Supports up to 3 PCI masters - Speed up to 33MHz
11. Two Card Bus Interface Support
12. Two USB 2.0 Host Port Support -
Supports HS, FS and LS
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